Session: 08-02: Micro/Nanoscale Heat Conduction

Paper Number: 132702

132702 - Thermal Boundary Conductance Mapping Across Bonded Heterogeneous Sic-Si Interface 

Abstract: 

The SOI wafer is widely used in the industry due to its low parasitic capacitance, catering to applications such as very-large-scale integration, photonics, MEMS, and radio-frequency chips. The commonly used SOI wafer consists of a silicon substrate, a buried SiO₂ layer providing electrical insulation, and a thin top silicon device layer where the electric devices are built. However, the low thermal conductivity of the SiO₂ layer impedes the efficient heat dissipation from the top silicon layer to the substrate, leading to a significant temperature rise. This issue becomes particularly critical in specialized applications like space technology and high-power-density scenarios, which negatively impacts device performance, reliability, and lifetime. To address this issue, a straightforward way is to replace the oxide layer by materials with high thermal conductivity. SiC emerges as a promising candidate as the substrate of silicon-on-isolator (SOI) wafers to achieve efficient thermal management due to its high thermal conductivity and large band gap. However, fabricating a silicon device layer on SiC substrate with high and uniform thermal boundary conductance (TBC) in wafer scale is challenging. In this work, a 4-inch Si-on-SiC wafer was fabricated utilizing a room-temperature surface-activated bonding method. Our wafer bonding sample demonstrated high quality, as few defects were observed using infrared microscopy. To enhance heat dissipation performance, we also conducted annealing at 750 ℃ on the sample. The structure and element constitution at the bonding interface were characterized by high resolution scanning transmission microscope. It is found that there are two amorphous layers, amorphous silicon and amorphous SiC, before annealing, while only the amorphous SiC layer remained after annealing. We analyzed the value and the distribution of strain/stress in the silicon device layer utilizing Raman mapping and high-resolution scanning transmission microscope image. Our findings indicated that the stress is small within our sample and has a negligible effect on the electric and thermal properties of silicon. As investigated by the time-domain thermoreflectance (TDTR) method, a TBC of 109 MW/m²K was achieved in the as-bonded sample, and was further promoted to 293 MW/m²K after an annealing process, which is a record value at Si/SiC interface via bonding method. To comprehend the enhancement, acoustic mismatch model, diffuse mismatch model, and thermal circuit model analysis were conducted. Those analyses suggest that the absence of the amorphous silicon layer and the interface between a-Si and a-SiC after annealing is the main reason for the increment in TBC. Furthermore, with the spatial TBC mapping and statistical analysis, we firstly demonstrate the spatial TBC analysis for SOI system, which can quantify the TBC distribution with the absence of the random noise of the experiment. Utilizing this approach, the spatial distribution of TBC before and after annealing were decided to be 7.5 MW/m²K and 49 MW/m²K, respectively. We attribute the spatial distribution to the roughness between the crystal part and the amorphous part and the uneven distribution of argon atoms. This TBC distribution investigation gives fruitful insight into the interfacial heat conduction and the corresponding fabricating process, significantly impacting practical thermal management applications.

Presenting Author: Junichiro Shiomi Institute of Engineering Innovation, The University of Tokyo

Presenting Author Biography: 1999
B.S., Mechanical Engineering, School of Engineering, Tohoku University
(1996 - 1997 University of California, Davis)
2004
Ph.D. in Mechanics, Royal Institute of Technology, Sweden (KTH)
2004 - 2007
JSPS Research Fellow (PD) (Affiliation: School of Engineering, The University of Tokyo)
2007 - 2008
Assistant Professor, Department of Mechanical Engineering, School of Engineering, The University of Tokyo
2008 - 2010
Lecturer, Department of Mechanical Engineering, School of Engineering, The University of Tokyo
2010 - 2017
Associate Professor, Department of Mechanical Engineering, School of Engineering, The University of Tokyo
2010 - 2011
Visiting Researcher, Department of Mechanical Engineering, Massachusetts Institute of Technology
2012 - 2015
JST PRESTO Researcher (concurrent)
2015 - 2020
Research Fellow, National Institute for Materials Science (concurrent)
2017 - Present
Professor, Department of Mechanical Engineering, School of Engineering, The University of Tokyo
2017 - present
Visiting Researcher, Center for Advanced Intelligence Project, RIKEN (concurrent)
2022 - Present
Professor, Institute of Engineering Innovation, School of Engineering, The University of Tokyo

Authors:

Rulei Guo Department of Mechanical Engineering, The University of Tokyo
Fengwen Mu Innovative Semiconductor Substrate Technology Co., Ltd.
Bin Xu Institute of Engineering Innovation, The University of Tokyo
Junichiro Shiomi Institute of Engineering Innovation, The University of Tokyo